In recent years, semiconductor devices have been adapted to afford multiple functions. Thus, there is a case where a plurality of power supply systems are arranged in one semiconductor device, and for each of the power supply systems, one or a plurality of circuits are arranged.
In a semiconductor device where an analog circuit and a digital circuit are mixed, there is a case where respective powers are supplied independently to the digital circuit and the analog circuit (in other words, a power supply system is divided), in order to prevent noise in the digital circuit from being transferred to the analog circuit.
In a transmitting/receiving portion in which a transfer of an input/output signal is performed through a signal line between circuits driven by different power supply systems, respectively, it is necessary to prevent a breakdown when an ESD (Electro-Static Discharge) stress is applied.
FIG. 25 is a diagram showing a configuration of a conventional semiconductor device in which, a plurality of different power supply systems are provided and the transfer of an input/output signal is performed through a signal line between circuits driven by the power supply systems, respectively (refer to Patent Document 1).
Referring to FIG. 25, a first circuit connected to a first power supply system comprises an analog section including an analog circuit (21), an output circuit (23), and an input protection circuit (25), for example. A second circuit connected to a second power supply system comprises a digital section including a digital circuit (22) and an input circuit (24). Both of the analog and digital sections are connected through a signal line (S11). To the analog section, power is supplied from a high potential side power supply terminal (Vdd1) and a low potential side power supply terminal (Vss1). To the digital section, power is supplied from a high potential side power supply terminal (Vdd2) and a low potential side power supply terminal (Vss2). The low potential side power supply terminal (Vss1) and the low potential side power supply terminal (Vss2) are connected via a protection element (HK1).
When the low-potential side power supply terminal (Vss2) is grounded and the ESD stress is applied from the high potential side power supply terminal (Vdd1) in this device, for example, a potential on a signal line (S11) increases through a PMOS transistor constituting the output circuit (23) because the PMOS transistor is in an unstable state. Since a source of an NMOS transistor in the input circuit (24) is grounded, a potential difference Vgs is generated between the source of the NMOS transistor and a gate of the NMOS transistor.
Since the gate-to-source voltage Vgs is the potential difference that is generated by the ESD stress application, this voltage may exceed a breakdown voltage for a gate oxide film of the NMOS transistor in the input circuit (24). Accordingly, this voltage may cause breakdown of the gate oxide film of the NMOS transistor in the input circuit (24).
The above description was directed to an operation when the low potential side power supply terminal (Vss2) is grounded, and the ESD stress is applied from the high potential side power supply terminal (Vdd1). When the high potential side power supply terminal (Vdd2) is grounded, and the ESD stress is applied from the high potential side power supply terminal (Vdd1) as well, a similar operation may cause the breakdown of the gate oxide film of the PMOS transistor in the input circuit (24).
As a measure for reducing such a damage, there is a method of inserting a protection element such as an NMOS transistor (HK3), which prevents breakdowns of gate oxide films of NMOS and PMOS transistors that constitute an input circuit (54), as shown in FIG. 26 (refer to Patent Document 1).
The NMOS transistor (HK3) is in an OFF state during a normal operation, and does not affect transmission of a signal between an output circuit (53) and the input circuit (54).
When the low potential side power supply terminal (Vss2) is grounded and the ESD stress is applied from the high potential side power supply terminal (Vdd1) in this device, for example, a potential on the signal line (S11) increases through the PMOS transistor that constitutes the output circuit (53). When the potential exceeds a predetermined potential difference or more, the NMOS transistor (HK3) is turned on, and the signal line (S11) thereby has substantially the same potential as the low potential side power supply terminal (Vss2). Thus, the breakdown of the gate oxide film caused by an excessive increase in a gate potential of the NMOS transistor in the input circuit (54) can be prevented.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-9-172146 (FIGS. 23 and 24, and the like)